High Speed VLSI Implementation of a Serial-in Parallel-Out Finite Field Multiplier | Asian Research

A 4-bit serial-in parallel-out finite field multiplier with high-speed VLSI implementation is shown. The multiplication is done using a recorded normal basis, which is a permutation of a type II optimal normal basis. Using pseudo NMOS multiplies, the multiplier was produced in 0.18 m CMOS technology. The multiplier was simulated and found to work correctly up to 0.5 GHz clock rate. In comparison to other CMOS logic structures, it was already built utilising area multiplies. The architecture has a relatively regular form, which makes using CMOS logic architectures to build VLSI much easier. The multiplier's performance was investigated using the Mentor graphics tool and the model parameters of a 0.18 m CMOS process.

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